Sequential non-deterministic detection in hardware design

ABSTRACT

The use of X&#39;s in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 61/689,347 filed Jun. 4, 2012. The entire disclosure of the above application is incorporated herein by reference.

FIELD

The present disclosure relates to automated verification and optimization of complex hardware designs.

BACKGROUND

Automating and scaling pre-silicon functional verification of state-of-the-art hardware designs, such as microprocessors and microcontrollers, presents many challenges. For example, the use of non-deterministic elements, commonly signified by X, for logic minimization and partial reset of large datapath registers can be effective in reducing the power and area consumption of certain logic in the chip. In certain cases, X's are also inserted to test hypothetical scenarios for improving coverage and other aspects of the design. However, the use of X's introduces verification challenges if not coupled with systematic methodologies and tools that can show that the non-determinism introduced by the X's does not propagate to the outputs of the design.

Sequential X refers herein to the problem of deciding if certain sampling points, including outputs, of an RTL design are deterministic, even with the presence of X's inside the design—referring to detecting the presence of Don't Cares, or X's, on these points. In this disclosure, a formal expression of the Sequential X problem is presented and algorithms which provide varying checking completeness are examined. Reveal-SEQX, an implementation of a Sequential X consistency checker which uses the Reveal model checker and a specialized correctness generator is also described. Further description of the Reveal model checker may be found in Automatic Formal Verification of Control Logic in Hardware Designs, Z. Andraus, Ph.D Dissertation, University of Michigan, April 2009. Reveal-SEQX is applied on a number of publicly available designs to reason about their output Don't Cares. Lastly, it is shown how the methodology and tool are used to avoid “good” X's appearing as false alarms, and to prove that the design is free of output X's.

This section provides background information related to the present disclosure which is not necessarily prior art.

SUMMARY

This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

A computer-implemented method is provided for verifying a hardware design for an electronic circuit. The method includes: providing a hardware design description for the electronic circuit; extracting a set of design elements from the hardware design description, where the set of design elements represent the electronic circuit in terms of signals and logical operations performed on the signals and the set of design elements includes deterministic elements having a value selected from zero or one and at least one non-deterministic element having a value denoted by a variable; assigning a first set of values to the deterministic elements of the electronic circuit; checking one or more sample points of the electronic circuit using the first set of values for the deterministic elements and across all possible values for the at least one non-deterministic element; and detecting non-determinism of the non-deterministic element on the one or more sample points of the electronic circuit when two values assigned to the at least one non-deterministic element yields different values at the one or more sampling points.

Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

DRAWINGS

The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

FIG. 1 is a diagram illustrating an example method for detecting non-determinism in a hardware design;

FIG. 2 is a diagram further illustrating the example method in which a designer is permitted to mark a register as Safe;

FIG. 3 is a flowchart depicting a general iterative methodology for verifying a hardware design;

FIG. 4 is a flowchart depicting an example method for verifying a hardware design;

FIG. 5 is a flowchart depicting a refined version of the methodology shown in FIG. 3.

Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings.

First, the behavior of a digital design is formalized using an intuitive notion that represents the design with hardware components reacting to input sequences. The emphasis is on the usage model and methodology rather than rigorous model checking or sequential equivalence checking theories. In a design with non-determinism due to partially initialized registers or the use of X in various forms, the values observed on the outputs are characterized with respect to determinism and whether the correct design description is sufficiently masking the non-determinism from the outputs.

A hardware design can be described as a tuple

V,INIT,Trans

, where V=I∪S∪C, and I is the set of input variables, S is the set of state-holding variables, and C is the set of intermediate combinational variables. Each variable is a vector of 1-bit components, and each can take the value of 0 and 1. Thus, the valuations of an n-bit variable belongs to {0, 1}^(n). With a fully initialized design and no use of X, the valuations of all the design variables are deterministically dependent on the inputs. Non-determinism is present when some components can take either 0 or 1 even if the inputs are fully specified. In this disclosure, this is referred to as X or Don't Care, interchangeably. A formal verification engine will exhaustively try 0 or 1 in place of the X, in order to determine certain properties. Therefore, the formal analysis is based solely on the {0, 1} domain.

Let

,

and

denote the sets of all possible valuations of S, C and I, respectively. INIT is a subset of

representing the group of initial states. Trans:

×

→

×

is a transition function such that (s′,c)=Trans (s, in) where s, in and c are the valuations of S, I and C respectively at the current time frame, and s′ is the valuation of S at the next time frame. We focus in this disclosure on designs with a single clock domain. In such designs, the succession of time frames is defined by the edges of the most frequent clock in the system.

Let M=

V,INIT,Trans

be a hardware design. Let (s₁, . . . , s_(n) _(s) ), (c₁, . . . , c_(n) _(c) ) and (i₁, . . . , i_(n) _(l) ) denote the elements of S, C and I respectively. Let proj_(s) (s,j) return the valuation of s_(j) under s. In other words s=

proj_(s) (s,1), . . . , proj_(s) (s,n_(s))

. Let proj_(c) and proj_(I) be defined similarly. Let val_(M) (s,in,v) denote the valuation of the variable v, given that the valuation of S is s, and the valuation of I is in. val_(M) is computed using the proj and Trans functions. Formally,

${{val}_{M}\left( {s,{in},v} \right)} = \left\{ \begin{matrix} {{{proj}_{s}\left( {s,j} \right)};} & {v = s_{j}} \\ {{{proj}_{I}\left( {{in},j} \right)};} & {v = i_{j}} \\ {{{proj}_{c}\left( {c,j} \right)};} & {{v = c_{j}},{{{where}\mspace{14mu} \left( {s^{\prime},c} \right)} = {{Trans}\left( {s,{in}} \right)}}} \end{matrix} \right.$

Given that, let val_(M) ^(k) be a generalization of val that takes into account the time frames of the design. Formally val_(M) ^(k) is defined recursively as follows:

val _(M) ⁰(s,in,v)=val _(M)(s,in,v)

val _(M) ^(k)(s,in ₁ ,in ₂ , . . . ,in _(k+1) ,v)=val _(M) ^(k-1)(s′,in ₂ , . . . ,in _(k+1) ,v); where(s′,c)=Trans(s,in ₁)

In words, val_(M) ^(k)(s, in₁, in₂, . . . , i_(k+1), v) is the valuation of the variable v at the current time frame, the input at the current time frame is in_(k+1).

Let M=

V,INIT,Trans

be a hardware design. Let equal^(k): INIT²×

^(k+1)×(I∪S∪C)→{true, false} be a function defined as equal_(M) ^(k)(s₀ ¹, s₀ ², in₁, . . . , in_(k+1), var)≡val_(M) ^(k)(S₀ ¹, in₁, . . . , in_(k+1), var)=val_(M) ^(k)(s₀ ², in₁, . . . , in_(k+1) var). If we let

=(o₁, . . . , o_(n)

)ε(I∪S∪C)^(n)

denote the vector of outputs, then equal_(M) ^(k)(s₀ ¹, s₀ ², in₁, . . . , in_(k+1), o_(j)) is true for any input sequence and any two initial states if and only if, the input sequence cannot differentiate between the initial states based on the valuation of o_(j). In many practical cases, a generalized notion of output equivalence is more suitable; each output is “guarded” by a valid bit, which determines whether the value on that output should necessarily be deterministic. In this disclosure, it is assumed, without loss of generality, that each output signal has a valid bit; an output signal without a valid bit can be described as an output signal with a valid bit set to the constant true; for this purpose, val (s,in,true)=true for any sε

ε and in ε

. The following generalizes the definitions of value to valid-value which takes into account the valid bit (if invalid, value is assumed to be 0), and of valid-equal to be the analogue of equal. Let

V=(ov₁, . . . , ov_(n)

)⊂(I∪S∪C∪{true})^(n)

denote the vector of the valid bits, where ov_(i) is the valid bit of o_(i).

Let valid−value_(M) ^(k)INIT×

^(k+1)×(I∪S∪C∪{true})×(I∪S∪C)→{true,false}×

be defined as follows:

valid − value_(M)^(k)(s₀, in₁, …  , in_(k + 1), valid, var) = val_(M)^(k)(s₀, in₁, …  , in_(k + 1), valid), value); where  value = val_(M)^(k)(s₀, in₁, …  , in_(k + 1), valid)?val_(M)^(k)(s₀, in₁, …  , in_(k + 1), var):  0

Let valid−equal_(M) ^(k):INIT²×

^(k+1)×(I∪S∪C∪{true})×(I∪S∪C)→{true, false} be a function such that valid−equal_(M) ^(k)(s₀ ¹, s₀ ², in₁, . . . , in_(k+1), valid, var)=true if and only if valid−value_(M) ^(k)(s₀ ¹, in₁, . . . , in_(k+1), valid, var)=valid−value_(M) ^(k)(s₀ ², in₁, . . . , in_(k+1), valid, var)

Informally, if the design starts from the initial state s₀ ¹ or s₀ ² and gets the input sequence in₁, . . . , in_(k+1), the valuation of the valid bit “valid” should be the same, and if so the valuation of the variable “var” is the same as well.

Using this notation, a design with internal non-determinism has no asymptotically observable don't-cares if valid-equal can be established for all design outputs starting at a given time frame. As defined formally in the following definition:

-   -   Definition 1. A hardware design M is valid outputs consistent at         (after)k₀, denoted by VOutput-Consistent-At (After) (M,k₀), if         the following holds for k=k₀(∀k≧k₀):

∀_(j)ε{1, . . . ,n

},∀s ₀ ¹ ,s ₀ ²εINIT,∀in ₁ , . . . ,in _(k+1)ε

valid−equal_(M) ^(k)(s ₀ ¹ ,s ₀ ² ,in ₁ , . . . ,in _(k+1) ,ov _(j) ,o _(j))

Informally, a hardware design passes VOutput-Consistent-After (M,k₀), if after getting k≧k₀ inputs, the valuations of the valid bits are not affected by the initial state, and if a valid bit ov_(i) valuation is true, the valuation of o_(f) is not affected by the initial state.

Given a design M=

V,INIT,Trans

and k₀, the goal is to determine whether VOutput-Consistent-After (M,k₀) is true. This, in turn, proves that there are not observable don't-cares on the outputs starting at time frame k₀ for the given reset sequence.

This goal is equally applicable for chip-level and block-level descriptions. When performing analysis at the level of the chip, and particularly for microprocessors and micro-controllers, designers are often forced to differentiate between “good” and “bad” don't-cares on the outputs. For example, CPU designs are generally characterized by architectural and non-architectural elements, and a set of specification (ISA) that defines how the processor reacts to executing programs (i.e. their effect on the architectural elements from a programmer viewpoint), and defines environment constrains including legal versus illegal input sequences or programs. If a microprocessor design contains an unintialized architectural element, inconsistency will generally arise; the executing program may read the value of an uninitialized architectural element before writing to it, and in turn introduce an X on the output that would otherwise be absent if the program is legal. This imposes restrictions on the types of don't-cares that are acceptable on the outputs. For this purpose, it is suggested that the following alternative consistency criterion which takes into account the legality of the input.

-   -   Definition 2. A hardware design M is legally consistent at         (starting from) k₀, denoted by Legally-Consistent-At (After)         (M,k₀), if the following holds for k=k₀(∀k≧k₀):

∀jε{1, . . . ,n

},∀s ₀ ¹ ,s ₀ ²εINIT,∀in ₁ , . . . ,in _(k+1)ε

:

legal(in ₁ , . . . ,in _(k+1))

valid−equal_(M) ^(k)(s ₀ ¹ ,s ₀ ² ,in _(k+1) ,ov _(j) ,o _(j))

Where legal:

*→boolean returns true if and only if according to the specification of the design behavior the input sequence is well defined and a valid output is expected to react to it. The function legal is usually infeasible to accurately define in a way that allows practical reasoning approaches to yield meaningful results. In the following section, a methodology is presented that allows the user to (partially) define the legality of an input stream either through invariants or properties imposed directly on the input stream or through imposing constraints on the design components that affect the propagation of don't-cares.

An efficient realization of the Sequential X detection system relies on duplicating the design in order to allow simultaneous examination of different assignments to non-deterministic components, while exhaustively examining all possible combinations of the deterministic components that drive values to the circuit (inputs and state initializations). Given a design D that is being checked for X consistency, two instances of the design D₁ and D₂ are created. Across the two instances, components with deterministic values are tied, including inputs and register initialization, while allowing non-determinism for others by leaving them duplicated. A component is marked as “Safe-X” if its corresponding components are tied together so that X originating from them are not leading to violating the consistency check. The following describes the general case where only inputs are marked as Safe.

With reference to FIG. 1, the most generic X check allows for a qualifier or valid bit, which indicates when X is allowed. For each observation point o_(j), with a valid bit ov_(j), let o¹ _(j), o² _(j) be correspond to o_(j) in D₁, D₂, and ov¹ _(j) corresponds to ov_(j) in D₁, then the wire o_(j—)consistent=ov¹ _(j)?(o¹ _(j)==o² _(j)):1′b1 is used to model the function at the observation point, and the conjunction of all the wires is defined as outputs_consistent=

_(j=1) ^(j=n)

o_(j—)consistent. Checking that outputs_consistent=true indicates that no X is shown on the observable points. This check can be done with any model checker.

Methodology for approximating legal X behavior is further described below. One can use Definition 1 as a first order approximation for the consistency criterion in Definition 2 assuming a tautological “legal” function. In this case, valid-equal will generally fail and return a witness showing an X on the output; in other words, a don't-care originating from an uninitialized element and propagating to the output. Diagnosing this case may determine that it is a “good” don't-care, and as a result there is a need for fixing a bug in the design logic, or ignoring the X showing on the output, or permanently resetting the source state element and paying a certain cost of area and power. Otherwise, this is a “bad” don't-care, i.e., a false alarm originating particularly from architectural elements. To eliminate this, the designer may decide to reset the register for verification purposes, but this may mask bugs that are otherwise present in the original design. Instead, this methodology allows the user to mark the register as “Safe” for X purposes.

The methodology allows the designer to mark an X-generating register as Safe, by checking whether all the outputs are consistent given that the subset S_(safe) ⊂S is initialized consistently to a random value. In most practical cases, choosing S_(safe)={uninitialized architectural registers} will prune out “false alarms” in which don't-care values are being propagated from free architectural elements. We will next present the formal definition for this criterion, analyze its relation to the previous criterion, and address its limitations and ways to improve upon it.

-   -   Definition 3. A hardware design M is S_(safe) safe X consistent         at (starting from)k₀, where S_(safe) ⊂S, denoted by         Safe-X-Consistent-At (After) (M,k₀,S_(safe)), if the following         holds for k=k₀(∀k≧k₀):

∀_(j)ε{1, . . . ,n

},∀s ₀ ¹ ,s ₀ ²εINIT,∀in ₁ , . . . ,in _(k+1)ε

:

UA−legal(in ₁ , . . . ,in _(k+1))

[consistent(s ₀ ¹ ,s ₀ ² ,S _(safe))

OA−legal(in ₁ , . . . ,in _(k+1))]

valid−equal_(M) ^(k)(s ₀ ¹ ,s ₀ ² ,in ₁ , . . . ,in _(k+1) ,ov _(j) ,o _(j))

Where consistent is a relation such that consistent (s₀ ¹,s₀ ²,S_(safe))

∀s_(j)εS_(safe): proj_(s)(S₀ ¹,j)=proj_(s)(s₀ ²,j), U A−legal is an under-approximation of the function legal (i.e. U A−legal⊂legal), and O A−legal is an over-approximation of the function legal (i.e., legal⊂O A−legal). Under-approximations are usually added by restricting inputs through constant assignment or adding assumptions on a group of inputs or design elements. Over-approximations are usually specified through invariants that were previously proven for the design.

With reference to FIG. 3, an iterative methodology is described in which the designer modifies the design to prune out the false counterexamples by initializing some uninitialized registers or marking them as safe, and tries to minimize the number of reset registers. Assume that each state element s_(j)εS has a type t_(i)ε{free,safe,reset} and s_(reset)εINIT be the reset state. In this case S_(safe) is equivalent to {s_(j)εS:t_(j)=safe}. Given the vector t, and the reset state s_(reset)εINIT (the state in which the design will be when all the registers are reset), let apply (M=

V,INIT,Trans

,s_(reset), t) be a function that applies the reset values from s_(reset) onto the state elements. Formally, apply (M=

V,INIT,Trans

,s_(reset), t) returns M′=

V,INIT′,Trans

, where INIT′={s₀εINIT|∀j:(t_(j)=reset)

proj_(s)(s₀,j)=proj_(s)(s_(reset),j)}.

Given over- and under-approximations of the function legal, the type of each register, and k₀ provided by the user, the design is first checked for consistency via the Safe-X-Consistent-After criterion applied on the design (registers are either reset, marked as safe, or left uninitialized). If the check fails, a counterexample is generated alongside a list of registers that are contributing to the X's showing on the outputs. Based on that and the knowledge about the design, the user can determine whether this is a false alarm involving illegal input or a genuine case indicating a potential bug in the design or lack of reset. The user may then update the type map and the approximations and re-iterate, or invoke an algorithm that computes a minimal set of registers whose reset can eliminate the X from the outputs, which helps in updating the type map and the approximations. The formulation of this process, which is also relevant in the case that the consistency check passes (need to minimize the registers being reset), is explained in the next sub-section. Provided the set S_(safe) that was created incrementally (through interactive work with the tool) or a-priori, and after automatically minimizing the reset subset, the user may want to diagnose the proof for false positives, or minimize the reset subset further based on the design knowledge and input legality. For each Safe register s_(j) the Safe-X proof is re-run after setting t_(j) to free, if no counterexample is found, the register s_(j) should not be in S_(safe); otherwise, the counterexample is displayed, at which point the user can update the over approximation if the counterexample is “bad”, or fix the design if it is a “good” counterexample.

This methodology provides a framework for an automated Safe X consistency check method. The method also allows over and under approximations to be used to constrain the design behavior. Furthermore, this method enables minimizing the initialization of registers for the purpose of saving area and power, while checking that adding X as a result of non-initialization does not lead to undesired observable X. An example of implementing the third method using the X consistency check is by iteratively and exhaustively un-initializing registers that are initialized in the original circuit, and for each un-initialization combination, the X consistency check is applied. If the proof passes in a given iteration, the register(s) that were purposely un-initialized introduced an X that was not observable on the sample points, and thus can be left without initialization in the original circuit. In other words, the X consistency check is not only a method for validating the current initialization and lack thereof (which introduces X), but also improving the circuit to further introduce safe X values that save area and power.

FIG. 4 provides an overview of a computer-implemented method for verifying a hardware design in accordance with this disclosure. In an example embodiment, a hardware design description is provided at 41 for an electronic circuit using a hardware description language, such as Verilog. It is readily understood that other representation of the electronic circuit are contemplated by this disclosure.

A set of design elements is first extracted at 42 from the hardware design description, where the set of design elements represent the electronic circuit in terms of signals and logical operations performed on the signals. For example, design elements may include but are not limited to gates, flip-flops, etc. The set of design elements may include deterministic elements and non-deterministic elements, where a deterministic element has a value selected from zero or one and a non-deterministic element has a value denoted by a variable, such as X. For illustration purposes, a deterministic element may be an initialized register, while a non-deterministic element may be a non-initialized register.

One or more sample points of the electronic circuit are then checked as indicated at 44. Referencing the notation above, VOutput-Consistent-After (M,k_(—)0) can be proven with any model checker. To do so, a first set of values are assigned to each deterministic element of the electronic circuit. The electronic circuit is then checked across all possible values for the non-deterministic elements. For a given non-deterministic element, non-determinism is indicated when two values assigned to the given non-deterministic element yield different values at one or more sampling points. The process may be iterated as necessary (e.g., exhaustively unless prevented by constraints) using a different set of values of the deterministic elements of the circuit. As noted above, this method is not limited to any particular type of model checker.

The remainder of this disclosure describes a more efficient approach that examines non determinism on intermediate points in the design, such as state holding variables. For a given hardware design D that is being checked, two instances of the design D₁, D₂ . . . D_(n), are created. For each state holding variable s_(i), let s¹ _(j), s² _(j) be correspond to s_(j) in D₁, D₂, then the wire s_(j—)consistent=(s¹ _(j)==s² _(j)) is used to indicate that the state holding variable is consistent, and the conjunction of all the wires is defined as states_consistent=

_(j=1) ^(j=n)

s_(j—)consistent. Algorithm 1 shows how this is done using an auxiliary method that checks states_consistent starting at a given cycle k₀.

An example of an improved implementation given in Algorithm 2 borrows the concept of “valid bits” to state elements, such that s_(j—)consistent=sv¹ _(j)?(s¹ _(j)==s² _(j)):1′b1. The logic representation of the valid bits is dependent on the circuit at hand. The algorithm uses an inductive argument based on the valid bits as a way to temporally abstract the behavior of the design with respect to non-determinism in the registers. The variation given in Algorithm 3 describes the case where valid bits are used in conjunction with marking registers as Safe-X.

-   -   Definition 4. A hardware design M is state consistent at k′,         denoted by State-Consistent-At (M,k′), if the following holds         for k=k′:

∀s ₀ ¹ ,s ₀ ²εINIT,∀in ₁ , . . . ,in _(k+1) ε

,∀jε{1, . . . ,n _(s)}:

val _(M) ^(k)(s ₀ ¹ ,in ₁ , . . . ,in _(k+1) ,s _(j))=val _(M) ^(k)(s ₀ ² ,in ₁ , . . . ,in _(k+1) ,s _(j))

Informally, if we start from any initial state and get any k₀ inputs, the valuation of S will be independent of the initial state. Assertion 1. ∀kε

: State-Consistent-At (M,k)

VOUTPUT−Consistent−At(M,k)

Assertion 2.

((∀kε{k₀, k₀+1, . . . , k′} VOutput-Consistent-At (M,k))

State-Consistent-At (M,k′))

VOutput-Consistent-After (M,k₀) The following algorithm is based on assertions (1) and (2), which can be shown trivially. It attempts to find a pivotal k′ that satisfies assertion (2). If the algorithm is unable to find such a k′, it will attempt to prove that ∀kε{k₀, k₀+1, . . . , k_(max)}: VOutput-Consistent-At (M,k), where, k_(max) is a given parameter.

Algorithm 1 For k′ ← k₀ to k_(max) If (! (VOutput-Consistent-At (M, k′))) print “The design is not consistent starting from k₀” return 0 If (State-Consistent-At (M, k′)) print “The design is consistent starting from k₀” return 1 print “The design is consistent ∀k ∈ {k₀, k₀ + 1, ... , k_(max)}.″ return 2 Algorithm 1 passes on two illustrative examples as will be described below. On real-life designs, however, a modified version of Algorithm 1 was used in order to achieve a proof with unbounded depth. Similarly to the outputs, it uses “valid bits” for the state-holding variables, and attempts to prove an invariant on the state-holding variables that can lead to convergence on verifying the property. Note also that Algorithm 1 assumed no X on inputs or wires. Algorithms 2 and 3 below make no such assumptions.

Without loss of generality, assume that each state-holding variable has a valid bit. Let SV=(sv₁, . . . , sv_(ns))⊂(I∪S∪C∪{true})^(n) ^(s) denote the vector of the valid bits, where sv_(j) is the valid bit of s_(j).

-   -   Definition 5. A hardware design M is valid states consistent at         k′, denoted by VState-Consistent-At (M,k′), if the following         holds for k=k′:

∀s ₀ ¹ ,s ₀ ²εINIT,∀in ₁ , . . . ,in _(k+1) ε

∀jε{1, . . . ,n _(s)}

valid−equal_(M) ^(k)(s ₀ ¹ ,s ₀ ² ,in ₁ , . . . ,in _(k+1) ,sv _(j) ,s _(j))

-   -   Definition 6. A hardware design M satisfies the Valid state         consistent invariant, denoted by VState-Consistent-Invariant         (M), if the following holds ∀{circumflex over (k)}ε         :

(Vstate-Consistent-At(M,{circumflex over (k)}))

(VState-Consistent-At(M,{circumflex over (k)}+1))

-   -   Definition 7. A hardware design M satisfies the unobservable X         invariant, denoted by Unobservable-X-Invariant (M), if the         following holds ∀{circumflex over (k)}ε         :

(VState-Consistent-At(M,{circumflex over (k)}))

(VOutput-Consistent-At(M,{circumflex over (k)}))

-   -   Definition 8. A hardware design M is inductively consistent,         denoted by IC (M), if the following holds:

(VState-Consistent-Invariant(M)

Unobservable-X-Invariant(M)

Assertion 3.

((∀kε{k₀, k₀+1, . . . , k′}:VOutput-Consistent-At(M,k))

VState-Consistent-At(M,k′)

IC (M))

VOutput-Consistent-After (M,k₀) The following algorithm is based on assertion (3), which can be shown trivially. It attempts to find a pivotal k′ such that VState-Consistent-At (M,k′) holds. If such a k′ is found, and IC (M) holds, then the design is consistent starting from k₀. Otherwise, it will attempt to prove that ∀kε{k₀, k₀+1, . . . , k_(max)}:VOutput-Consistent-At (M,k), where k_(max) is a given parameter.

Algorithm 2 VOutput-Consistent-After-Test (M, k₀, k_(max)) (01) k′ ← k₀ (02) While (k′ ≦ k_(max)) (03) If (!( VOutput-Consistent-At (M, k′))) (04) print “The design is not consistent starting from k₀″ (05) return 0 (06) If ( VState-Consistent-At (M, k′)) (07) break (08) k′ ← k′ + 1 (09) If(k′ ≦ k_(max) && IC (M)) (10) print “The design is consistent starting from k₀″ (11) return 1 (12) While (k′ ≦ k_(max)) (13) If (! (VOutput-Consistent-At (M, k′))) (14) print “The design is not consistent starting from k₀” (15) return 0 (16) k′ ← k′ + 1 (17) print “The design is consistent ∀k ∈ {k₀, k₀ + 1, ... , k_(max), }” (18) return 2

Without loss of generality, in what follows we will extend the previous algorithms for the cluster of designs that are “consistently initialized”, as defined below, for the purpose of safe-X.

-   -   Definition 9. Let M be a hardware design. s_(j) is a         consistently initialized state−holding variable, denoted by         Consistently-Initialized-Variable (M,s_(j)) if the following         holds:

∀s ₀ ¹ ,s ₀ ²εINIT:proj_(s)(s ₀ ¹ ,j)=proj_(s)(s ₀ ² ,j)

Informally, s_(j) is a consistently initialized state−holding variable, if its valuations in all of the initial states are the same.

-   -   Definition 10. Let M be a hardware design. s_(j) is a free−state         holding variable, denoted by Free-Variable (M,s_(j)), if INIT is         closed under changes in the value of s_(j), Formally:

∀s ₀ ¹εINIT,∀yε

_(j) ,∃s ₀ ²εINIT:

proj_(s)(s ₀ ² ,j)=y

∀lε{1, . . . ,n _(s) }\{j}:proj_(s)(s ₀ ¹ ,l)=proj_(s)(s ₀ ² ,l)

Where

_(j), denotes the set of all possible valuations of s_(j).

Here is an example illustrating Definitions 9 and 10:

reg s₁, s₂, s₃, flag; initial begin s₁ = 0; //s₁ i consistently initialized. //s₂ is free. if (flag)s₃ = 0; //s₃ and flag are neither consistently initialized nor free. end

-   -   Definition 11. Let M be a hardware design. M is consistently         initialized, denoted by Consistently-Initialized (M), if the         following holds:

∀s _(j) εS: Consistently-Initialized-Variable(M,s _(j))

(M,s _(j))

Free−Variable(M,s _(j))

Denote the set of all the free state-holding architectural variables of a microprocessor design CPU by

R. Formally

={s_(j)εS∩R:Free-Variable (CPU,s_(j))}. Let

denote the set of all possible valuations to the set

R. While reference is made to a microprocessor, it is understood that the concept described herein are not limited thereto and is applicable to any hardware design or portions thereof

Let the function reg-map (CPU, fr), where CPU=

V,INIT,Trans

is a microprocessor design, and frε

, return CPU′=

V,INIT′,Trans

, where INIT′={s₀εINIT|the valuation of

R in s₀ is fr}.

Assertion 4. Safe-X-Consistent-After (CPU,k₀)

∀frε

Consistent-After(reg-map(CPU,fr),k₀).

The RHS of assertion 4 can be checked by applying algorithm 2 with the reg-map option of reveal for an arbitrary fr₀ε

.

Algorithm 3 Safe-X-Consistent-After-Test (M, k₀, k_(max)) Results = {VOutput-Consistent-After-Test (reg-map (CPU, fr), k₀, k_(max))|fr ∈ 

If (0 ∈ Results) print “The design is not consistent starting from k₀” return 0 If (2 ∈ Results) print “The design is consistent ∀k ∈ (k₀, k₀ + 1, ... , k_(max)}”. return 2 print “The design is consistent starting from k₀” return 1

The methodology described in FIG. 5 refines the one shown in FIG. 3 based on Algorithm 3. The Safe-X-Consistent-After now results in either successfully proving the property, or failing due to two possible reasons; failure due to a legitimate counterexample, or failure due to a negative result in the induction (in which case Reveal-SEQX reports success for bounded equivalence with k_(max)). The rest of the flow is similar in the earlier case, while in the latter, an automatic algorithm can be used to update the valid bits.

The Reveal-SEQX application integrates an implementation of Algorithm 3 and the Reveal model checker, based on the configuration in FIG. 2. The algorithm was run on a 64-bit Alpha processor, a 5-stage pipeline where much of the internal state is reset. The design is intended to have a register file attached to inputs and outputs of the core, but due to the nature of the Sequential X algorithm, we did not need to supply a safe-x list. The design is Safe-X consistent with k₀=4 and an empty S_(safe). It also has been applied on a publicly available MIPS core, which is also a 5-stage pipeline, and contains 1615 single-bit registers, with S_(safe) consisting of the architectural memories and the registers file. The run time for these examples on a machine with Intel Core i7 CPU 860 at 2.80 GHz and 8 GB memory is seconds to show a witness for an X bug, and minutes for a full proof.

The techniques described herein may be implemented by one or more computer programs executed by one or more processors. The computer programs include processor-executable instructions that are stored on a non-transitory tangible computer readable medium. The computer programs may also include stored data. Non-limiting examples of the non-transitory tangible computer readable medium are nonvolatile memory, magnetic storage, and optical storage.

Some portions of the above description present the techniques described herein in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. These operations, while described functionally or logically, are understood to be implemented by computer programs. Furthermore, it has also proven convenient at times to refer to these arrangements of operations as modules or by functional names, without loss of generality.

Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain aspects of the described techniques include process steps and instructions described herein in the form of an algorithm. It should be noted that the described process steps and instructions could be embodied in software, firmware or hardware, and when embodied in software, could be downloaded to reside on and be operated from different platforms used by real time network operating systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored on a computer readable medium that can be accessed by the computer. Such a computer program may be stored in a tangible computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, application specific integrated circuits (ASICs), or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus. Furthermore, the computers referred to in the specification may include a single processor or may be architectures employing multiple processor designs for increased computing capability.

The algorithms and operations presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may also be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatuses to perform the required method steps. The required structure for a variety of these systems will be apparent to those of skill in the art, along with equivalent variations. In addition, the present disclosure is not described with reference to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

The present disclosure is well suited to a wide variety of computer network systems over numerous topologies. Within this field, the configuration and management of large networks comprise storage devices and computers that are communicatively coupled to dissimilar computers and storage devices over a network, such as the Internet.

The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. 

What is claimed:
 1. A method executed by a computer having at least one processor, wherein the processor execute machine-readable instructions to implement the method comprising: retrieving a design description having some combination of logical and memory elements, communicatively coupled to each other; associating one or more states corresponding to an initial input value, an output and a cycle number, for each of the possible input values corresponding to the design description; and detecting a subset of the one or more associated states, wherein the detected subset of the one or more associated of states, is based at least in part on an identification of determinism and an evaluation criteria.
 2. A method of claim 1, wherein the step of detecting a subset of the one or more of states further comprises: identifying a group of initial input values for which, the corresponding states wherein the corresponding states based at least in part on an evaluation of determinism.
 3. A method of claim 1, wherein the identification of determinism further comprises: generating input values for the design description and inputting the generated input values; generating output values for the design description over one or more trials for the same input value; and identifying a discrepancy between one or more generated output values corresponding to the same generated input value.
 4. A method of claim, wherein the detected subset of the one or more states further comprises: identifying a value indicative of the cycle number, for a given initial input value, wherein the value indicative of the cycle number corresponds to the identification of determinism.
 5. A method of claim 1 further comprising: retrieving one or more conditions, wherein the corresponding states have any combination of deterministic and non-deterministic states.
 6. The method of claim 1 further comprising: receiving input, from a user, identifying one or more states corresponding to any combination of deterministic and non-deterministic outputs. Generating instructions corresponding to the identified one or more states, wherein the generated instructions correspond to outputs having only deterministic elements.
 7. The method of claim 1 wherein the step of detecting the subset of states further comprising: detecting a first state, wherein the first state's outputs are indicative of non-determinism; and determining a subset of states, based at least in part on the first state, wherein the subset of the one or more states correspond to one or more behavioral conditions.
 8. The method of claim 1, wherein further comprises: detecting a subset of the one or more states, wherein the subset comprises deterministic outputs for all initial input values.
 9. The method of claim 1, wherein the step of detecting a subset of the one or more states further comprises: detecting a plurality of states, wherein the subset comprises non-deterministic outputs for all initial input values.
 10. The method of claim 1, wherein the step of detecting a subset of the one or more states further comprises: detecting a plurality of states, wherein the subset comprises non-deterministic outputs for all initial input values.
 11. The method of claim 1 further comprising: Generating instructions indicative of the behavioral conditions; and Selecting a subset of states, based at least in part on the generated instruction.
 12. The method of claim 1 further comprising: identifying boundary conditions, comprising initial input values and total number of iterations, wherein the subset of states comprise zero non-deterministic elements.
 13. A computer-executed module, wherein the module comprises executed by a computer having at least one processor, wherein the processor execute machine-readable instructions, wherein the module comprises: a design description having some combination of logical and memory elements, communicatively coupled to each other; an association module for one or more states corresponding to an initial input value, an output and a cycle number, for each of the possible input values corresponding to the design description; and a subset of the one or more associated states, wherein the subset of the oe or more states is outputted based at least in part an identification of determinism and an evaluation criteria.
 14. The module of claim 13, wherein the subset of the one or more associated states further comprises: one or more input values, wherein the one or more input values is identified based at least in part on an evaluation of determinism.
 15. The module of claim 13, wherein the subset of the one or more associated states further comprises: input values, generated for the design description; output values, generating for the design description, over one or more trials for the same input values; and a discrepancy between one or more generated output values corresponding to the same generated input value, wherein the discrepancy is identified based on a comparison.
 16. A module of claim 13, wherein the subset of the one or more associated states further comprises: a value indicative of the cycle number, for a given initial input value, wherein the value is indicative of the cycle number corresponds to the identification of determinism.
 17. A module of claim 13 further comprising: one or more conditions corresponding with the associated states, wherein the associated states based upon an evaluation of determinism.
 18. The module of claim 13 further comprising: an identification, received as input, from a user, identifying one or more associated states corresponding to any combination of deterministic and non-deterministic outputs; and Generated instruction wherein the generated instructions correspond to outputs having only deterministic elements.
 19. The module of claim 13 wherein the step of detecting the subset of states further comprising: a first state, wherein the first state's outputs are indicative of non-determinism; and outputted values indicative of the subset of states, wherein the subset of the one or more states correspond to one or more behavioral conditions.
 20. The module of claim 1, wherein further comprises: detecting a subset of the one or more states, wherein the subset comprises deterministic outputs for all initial input values. 